1. Field of the Invention
The present invention relates generally to the fabrication of semiconductor structures, and more specifically to the fabrication of copper, LowK dielectric, dual damascene structures.
2. Description of the Related Art
In the fabrication of semiconductor devices, integrated circuits are defined on semiconductor wafers by forming a plurality of layers over one another resulting in multi-level structures. As a result of the various layers disposed over one another, a surface topography of the wafer can become irregular, and an un-corrected irregularity increases with the number of subsequent layers deposited. Chemical Mechanical Planarization (CMP) has developed as a fabrication operation primarily utilized to planarize the surface topography of deposited layers, and to remove the overburden deposits. Additional fabrication operations including surface finish, buffing, insulator cleaning, etching, and the like, are also frequently accomplished using CMP processes and apparatus.
At the substrate level, transistor devices having diffusion regions are formed over and into silicon substrates. In subsequent levels, interconnect metallization lines are patterned and electrically connected to the transistor devices to define a desired functional device. As is well known, patterned conductive layers are insulated from other conductive layers by dielectric materials, such as silicon dioxide in conventional cases. At each metallization level there is a need to remove the overburden metal or to planarize dielectric material. Without planarization, fabrication of additional metallization layers becomes substantially more difficult due to the higher variations in the surface topography. In other major applications, metallization line patterns are formed in the dielectric material, then conductive material is deposited over the whole wafer surface, and finally, metal a CMP operation is performed to remove excess metallization, e.g., such as copper. An additional diffusion layer is normally deposited prior to conductor deposition to prevent diffusion of conductive material into the bulk of dielectric that deteriorates its insulating dielectric properties and poisons the transistors.
Copper dual damascene technology, and the technology of conductive material dual damascene structures, evolved into a process of choice for the integrated circuit industry. In copper dual damascene fabrication, the Cu-CMP is typically utilized for both copper and barrier overburden removal, as described below in references to FIGS. 1A-1C.
FIG. 1A shows a portion of a semiconductor wafer 10 with a typical copper dual damascene structure being fabricated therein. Features 14 such as trenches and vias have been fabricated into insulator 12. A barrier 18 has been deposited over the insulator 12 lining the features 14. Copper fill has been deposited in the features 14 resulting in copper overburden16 over barrier 18.
FIG. 1B shows the portion of semiconductor wafer 10 with the copper dual damascene structure being fabricated therein described in FIG. 1A after a first CMP process has been performed. The first CMP is performed to planarize the surface of the insulator 12 at the barrier 18. The copper overburden 16 shown in FIG. 1A is essentially removed, leaving only copper fill 16xe2x80x2 in features 14, and barrier 18 to make up the planarized surface. It should be appreciated that, up until the point of removal of the copper overburden (see FIG. 1A) exposing barrier 18, the surface being planarized by CMP is a homogenous material. As soon as barrier 18 is exposed, the surface becomes heterogeneous with both copper fill 16xe2x80x2 and barrier 18 material and chemical properties being processed by CMP.
FIG. 1C shows an ideal completion of a dual damascene structure fabricated in a portion of a semiconductor wafer 10. The ideal structure illustrated is the fabrication goal following a second CMP of the structure illustrated in FIG. 1B. Barrier 18 (see FIG. 1B) is removed leaving a planarized insulator surface including the insulator 12, a barrier liner 18xe2x80x2 of features 14, and the copper fill 16xe2x80x2 within features 14. It should be noted that number of materials with differing material and chemical properties processed by CMP in FIG. 1C is now three.
As is known, CMP was initially developed for, and is most effective and well suited for planarization of a non-planar homogenous (i.e., consisting of the same material) surface. Looking again at FIG. 1B, it should be appreciated that in final phases of the copper CMP, the surface is neither homogenous, nor is it in need of planarization. In typical copper dual damascene structure fabrication, CMP is the next process step to be performed on the structure, but it is not a structure well suited for CMP.
To planarize a surface, CMP implements a combination of chemical and abrasive action by applying a surface to be planarized against a processing surface having varying degrees of elasticity, varying degrees of abrasiveness, wetted with varying degrees of chemically aggressive slurry which also may contain varying degrees of abrasiveness, all according to process goals, process conditions, material and chemical properties, and the like. In the case of copper CMP, it is common practice to use a processing surface such as a pad with a high degree of hardness. Due to the typically hard insulator 12 underlying a copper dual damascene structure, pressure is generally also moderate to high, and the frictional contact generated between the processing surface and the surface to be planarized, results in generally high shear stress at the surface of the wafer.
Under the processing conditions just described, the point at which the copper overburden 16 (see FIG. 1) is removed and barrier 18 is exposed, the surface being processed by CMP is practically flat, however no longer homogenous, and the effectiveness of the CMP is dramatically reduced. Typically, it is at this point when the CMP process, and processing conditions are modified in order to remove barrier 18 with a second CMP process, but the heterogeneous surface including the hard barrier 18 and the soft copper 16xe2x80x2 are not optimally processed by the same CMP operation. Instead of the ideal structure illustrated in FIG. 1C, a typical semiconductor wafer is processed less precisely and results in less than ideal structures therein.
FIG. 1D illustrates a typical copper dual damascene structure reflecting structural flaws typical of heterogeneous CMP processing. CMP generally removes barrier 18 (see FIG. 1B) and leaves features 14 lined with barrier liner 18xe2x80x2 and copper filled 16xe2x80x2, but surface irregularities are noted such as dishing 20 in the copper fill 16xe2x80x2, and a less than planar surface 22 across the structure. The less than planar surface 22 typically also includes dielectric erosion 24. Additionally, because copper is a material of the structure, and it is a soft and reasonably chemically reactive material, preventing corrosion of the copper fill 16xe2x80x2, and scratching, are also serious fabrication challenges.
What is needed are methods and apparatus for copper, and other conductive material, dual damascene structure fabrication that exploit the advantages of CMP for planarization of the homogenous part of the overburden material, which is copper, and implement alternative fabrication processes better suited for heterogeneous surface processing. The methods and apparatus should be implemented to maximize manufacturing efficiency, and position the technology of dual damascene to better introduce and develop emerging related technologies.
Broadly speaking, the present invention fills these needs by providing a method for forming dual damascene structures in LowK dielectric insulators that utilizes CMP for those processes in which CMP is most effective, and etch for those processes better suited for etch fabrication. Additionally, methods of the present invention exploit emerging technologies for fabricating LowK and ultra-LowK dielectric structures. The present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, or a method. Several embodiments of the present invention are described below.
In one embodiment, a method for fabricating semiconductor structures on a insulator is disclosed. The method includes forming a LowK dielectric material over the insulator, and forming a capping film over the LowK dielectric material. Features are formed in the LowK dielectric material which have inner surfaces defined by the LowK dielectric material. The features define regions for receiving a conductive material. A barrier layer is formed over the capping film and over the surfaces of the features, and the features are filled with the conductive material. The filling of the features leaves an overburden amount of the conductive material. The method further includes performing a chemical mechanical planarization (CMP) operation to remove the overburden amount of the conductive material. The CMP operation is configured to be discontinued upon reaching at least part of the barrier layer. The method then performs a dry etch to remove the barrier layer. The dry etch is configured to expose at least part of the capping film. In another embodiment, a method for fabricating semiconductor structures on a insulator is disclosed. The method includes forming a LowK dielectric material over the insulator and then forming a capping film over the LowK dielectric material. The capping film is defined by at least two contiguously formed material layers. The method next forms features in the LowK dielectric material which have inner surfaces defined by the LowK dielectric material. The features define regions for receiving a conductive material. The method further includes forming a barrier layer over the capping film and over the surfaces of the features. The features are filled with the conductive material which leaves an overburden amount of the conductive material. Next, the method performs a chemical mechanical planarization (CMP) operation to remove the overburden amount of the conductive material. The CMP operation is configured to be discontinued upon reaching at least part of the barrier layer. The method continues by performing a first dry etch to remove the barrier layer to expose at least part of the capping film; and then performing a second dry etch to remove at least one of the contiguously formed material layers of the capping film.
In still a further embodiment, a method for removing a portion of overburden conductive material, barrier film and capping film in a semiconductor structure is disclosed. The semiconductor structure has a LowK dielectric material, which has features defined therein for forming conductive vias and conductive vias and trenches. Further, a top surface of the LowK dielectric material has a capping film, and a barrier film lines the features and is formed over the capping film. A conductive material fills the features and leaves a portion of overburden conductive material over the barrier film. The method includes first performing a chemical mechanical planarization (CMP) operation to remove the portion of overburden conductive material, and discontinuing the CMP operation when the portion of overburden conductive material is determined to be substantially removed. Next, the method includes moving the semiconductor structure to a plasma etching station and performing an initial plasma etch to remove the barrier film. The method then performs a follow-up plasma etch to remove at least part of the capping film. The method then includes determining if a next LowK dielectric layer is required. If the next LowK dielectric layer is required, a next LowK dielectric layer is formed and the method repeated.
The advantages of the present invention are numerous. One notable benefit and advantage of the invention is that CMP is exploited for fabrication operations well suited for CMP, and etch is utilized for those operations better suited for etch. The resulting structure is more precisely fabricated and with less scrap and defects.
Another benefit is the methods of the present invention accommodate the emerging technologies of ultra-LowK dielectrics, and are therefore capable of implementation as new materials and structures are introduced.